A conventional semiconductor device may include a p-type well region that isolates an element forming region, and a DMOS transistor that is formed in the element forming region. The semiconductor device may also include a p-type silicon substrate, n-type source and drain regions that are selectively formed on the silicon substrate and isolated from each other by a field oxide film, and a gate electrode that is formed on the silicon substrate with a gate oxide film interposed between the gate electrode and the silicon substrate. The field oxide film may be formed in the p-type well region.
In the semiconductor device having a conventional element isolation structure as described above, the DMOS transistor may be mounted together with other elements. Such a semiconductor device may include not only a wiring electrically connected to the DMOS transistor but also additional wirings electrically connected to different elements. Thus, different voltages, which are adapted for the different elements, respectively, may be applied to the additional wirings.
In this case, if the wirings pass near a field insulating film or intersect the field insulating film, an electric field from the wirings attracts anions in the semiconductor substrate to a region directly below the field insulating film (i.e., a surface of the p-type well region which separates the element forming region), causing a field inversion in the p-type well region. Thus, a region where the field inversion is caused may act as a leak path through which a leakage current may flow, which may result in an element isolation failure. Such a leakage current caused by the electric field from the wirings becomes more considerable when a voltage applied to the wirings increases.
To avoid the above problem, a device may be designed based on a design rule for forming wirings to be spaced apart from a field insulating film by a specified distance depending on the amount of voltages applied to the wirings. However, using this method, some areas of a semiconductor chip may not effectively be used and it may be difficult to further reduce the size of the semiconductor chip.